Use the header with DSI phy clock IDs to make code more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> --- Depends on: https://lore.kernel.org/all/20250127132105.107138-1-krzysztof.kozlowski@xxxxxxxxxx/ --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index e3f9c56a778cf8c64735ede1e85286bde12c1c87..7e119370f3375573e284587d48aef6dca3ed707f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interconnect/qcom,msm8974.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/clock/qcom,mmcc-msm8974.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -1871,10 +1872,10 @@ mmcc: clock-controller@fd8c0000 { <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <0>, <0>, <0>; @@ -1961,8 +1962,10 @@ mdss_dsi0: dsi@fd922800 { interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -2032,8 +2035,10 @@ mdss_dsi1: dsi@fd922e00 { interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, -- 2.43.0
