Hi Biju,
Thanks for the patch.
On Sun, Jan 26, 2025 at 01:46:03PM +0000, Biju Das wrote:
> The SD/MMC block on the RZ/G3E ("R9A09G047") SoC is similar to that
> of the RZ/V2H, but the SD0 channel has only dedicated pins, so we must
> use SD_STATUS register to control voltage and power enable (internal
> regulator).
>
> For SD1 and SD2 channel we can either use gpio regulator or internal
> regulator (using SD_STATUS register) for voltage switching.
>
> Document RZ/G3E SDHI IP support.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> .../devicetree/bindings/mmc/renesas,sdhi.yaml | 20 +++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> index af378b9ff3f4..ef3acf0f58e0 100644
> --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> @@ -68,6 +68,9 @@ properties:
> - renesas,sdhi-r9a08g045 # RZ/G3S
> - renesas,sdhi-r9a09g011 # RZ/V2M
> - const: renesas,rzg2l-sdhi
> + - items:
> + - const: renesas,sdhi-r9a09g047 # RZ/G3E
> + - const: renesas,sdhi-r9a09g057 # RZ/V2H(P)
>
> reg:
> maxItems: 1
> @@ -124,6 +127,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - renesas,sdhi-r9a09g047
> - renesas,sdhi-r9a09g057
> - renesas,rzg2l-sdhi
> then:
> @@ -211,6 +215,22 @@ allOf:
> sectioned off to be run by a separate second clock source to allow
> the main core clock to be turned off to save power.
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,sdhi-r9a09g047
> + then:
> + properties:
> + vqmmc-regulator:
> + type: object
> + description: VQMMC SD regulator
> + $ref: /schemas/regulator/regulator.yaml#
> + unevaluatedProperties: false
> +
> + required:
> + - vqmmc-regulator
> +
> required:
> - compatible
> - reg
> --
> 2.43.0
>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
