The SD/MMC block on the RZ/G3E ("R9A09G047") SoC is similar to that
of the RZ/V2H, but the SD0 channel has only dedicated pins, so we must
use SD_STATUS register to control voltage and power enable (internal
regulator).
For SD1 and SD2 channel we can either use gpio regulator or internal
regulator (using SD_STATUS register) for voltage switching.
Biju Das (7):
dt-bindings: mmc: renesas,sdhi: Document RZ/G3E support
clk: renesas: r9a09g047: Add SDHI clocks/resets
mmc: renesas_sdhi: Arrange local variables in reverse xmas tree order
mmc: renesas_sdhi: Add support for RZ/G3E SoC
arm64: dts: renesas: r9a09g047: Add SDHI0-SDHI2 nodes
arm64: dts: renesas: rzg3e-smarc-som: Enable SDHI{0,2}
arm64: dts: renesas: r9a09g047e57-smarc: Enable SDHI1
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 20 +++
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 57 ++++++++
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 65 +++++++++
.../boot/dts/renesas/renesas-smarc2.dtsi | 9 ++
.../boot/dts/renesas/rzg3e-smarc-som.dtsi | 89 ++++++++++++
drivers/clk/renesas/r9a09g047-cpg.c | 31 +++++
drivers/mmc/host/renesas_sdhi.h | 1 +
drivers/mmc/host/renesas_sdhi_core.c | 131 +++++++++++++++++-
drivers/mmc/host/tmio_mmc.h | 5 +
9 files changed, 407 insertions(+), 1 deletion(-)
--
2.43.0
