Hi Biju,
Thanks for your patch!
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node
>
> Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI
> and add icu as interrupt-parent of pincontrol.
>
> Also, define the ICU IRQs for board DT users.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
Cheers,
Fab
> ---
> arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 +++++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> index 133aa3272d3a..0beac052f208 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -8,6 +8,24 @@
> #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> +#define RZG3E_NMI 0
> +#define RZG3E_IRQ0 1
> +#define RZG3E_IRQ1 2
> +#define RZG3E_IRQ2 3
> +#define RZG3E_IRQ3 4
> +#define RZG3E_IRQ4 5
> +#define RZG3E_IRQ5 6
> +#define RZG3E_IRQ6 7
> +#define RZG3E_IRQ7 8
> +#define RZG3E_IRQ8 9
> +#define RZG3E_IRQ9 10
> +#define RZG3E_IRQ10 11
> +#define RZG3E_IRQ11 12
> +#define RZG3E_IRQ12 13
> +#define RZG3E_IRQ13 14
> +#define RZG3E_IRQ14 15
> +#define RZG3E_IRQ15 16
> +
> / {
> compatible = "renesas,r9a09g047";
> #address-cells = <2>;
> @@ -131,6 +149,95 @@ soc: soc {
> #size-cells = <2>;
> ranges;
>
> + icu: interrupt-controller@10400000 {
> + compatible = "renesas,r9a09g047-icu";
> + reg = <0 0x10400000 0 0x10000>;
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "nmi",
> + "port_irq0", "port_irq1", "port_irq2",
> + "port_irq3", "port_irq4", "port_irq5",
> + "port_irq6", "port_irq7", "port_irq8",
> + "port_irq9", "port_irq10", "port_irq11",
> + "port_irq12", "port_irq13", "port_irq14",
> + "port_irq15",
> + "tint0", "tint1", "tint2", "tint3",
> + "tint4", "tint5", "tint6", "tint7",
> + "tint8", "tint9", "tint10", "tint11",
> + "tint12", "tint13", "tint14", "tint15",
> + "tint16", "tint17", "tint18", "tint19",
> + "tint20", "tint21", "tint22", "tint23",
> + "tint24", "tint25", "tint26", "tint27",
> + "tint28", "tint29", "tint30", "tint31",
> + "int-ca55-0", "int-ca55-1",
> + "int-ca55-2", "int-ca55-3",
> + "icu-error-ca55",
> + "gpt-u0-gtciada", "gpt-u0-gtciadb",
> + "gpt-u1-gtciada", "gpt-u1-gtciadb";
> + clocks = <&cpg CPG_MOD 0x5>;
> + power-domains = <&cpg>;
> + resets = <&cpg 0x36>;
> + };
> +
> pinctrl: pinctrl@10410000 {
> compatible = "renesas,r9a09g047-pinctrl";
> reg = <0 0x10410000 0 0x10000>;
> @@ -140,6 +247,7 @@ pinctrl: pinctrl@10410000 {
> gpio-ranges = <&pinctrl 0 0 232>;
> #interrupt-cells = <2>;
> interrupt-controller;
> + interrupt-parent = <&icu>;
> power-domains = <&cpg>;
> resets = <&cpg 0xa5>, <&cpg 0xa6>;
> };
> --
> 2.43.0
>
