Re: [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650

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On 1/16/2025 5:24 PM, neil.armstrong@xxxxxxxxxx wrote:
Hi,

On 16/01/2025 10:11, Ziqi Chen wrote:
Use Operation Points V2 for UFS on SM8650 so that multi-level
clock/gear scaling can be possible.


I've already sent a similar one at https://lore.kernel.org/all/20250115-topic-sm8x50-upstream-dt-icc-update-v1-10-eaa8b10e2af7@xxxxxxxxxx/

Neil


Hi Neil,

Thank you for reminder , I will withdraw this patch in next version.

- Ziqi


Co-developed-by: Can Guo <quic_cang@xxxxxxxxxxx>
Signed-off-by: Can Guo <quic_cang@xxxxxxxxxxx>
Signed-off-by: Ziqi Chen <quic_ziqichen@xxxxxxxxxxx>
---
  arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 +++++++++++++++++++++++-----
  1 file changed, 43 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 01ac3769ffa6..5466f1217f64 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2557,18 +2557,11 @@ ufs_mem_hc: ufs@1d84000 {
                        "tx_lane0_sync_clk",
                        "rx_lane0_sync_clk",
                        "rx_lane1_sync_clk";
-            freq-table-hz = <100000000 403000000>,
-                    <0 0>,
-                    <0 0>,
-                    <100000000 403000000>,
-                    <100000000 403000000>,
-                    <0 0>,
-                    <0 0>,
-                    <0 0>;
              resets = <&gcc GCC_UFS_PHY_BCR>;
              reset-names = "rst";
+            operating-points-v2 = <&ufs_opp_table>;
              interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
                       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
                      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
@@ -2590,6 +2583,48 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
              #reset-cells = <1>;
              status = "disabled";
+
+            ufs_opp_table: opp-table {
+                       compatible = "operating-points-v2";
+                       // LOW_SVS
+                       opp-100000000 {
+                               opp-hz = /bits/ 64 <100000000>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <100000000>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>;
+                               required-opps = <&rpmhpd_opp_low_svs>;
+                       };
+
+                       // SVS
+                       opp-201500000 {
+                               opp-hz = /bits/ 64 <201500000>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <201500000>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>;
+                               required-opps = <&rpmhpd_opp_svs>;
+                       };
+
+                       // NOM/TURBO
+                       opp-403000000 {
+                               opp-hz = /bits/ 64 <403000000>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <403000000>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>,
+                                       /bits/ 64 <0>;
+                               required-opps = <&rpmhpd_opp_nom>;
+                       };
+               };
          };
          ice: crypto@1d88000 {





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