On Wed 08 Jan 2025 at 17:40, Jian Hu <jian.hu@xxxxxxxxxxx> wrote:
> Add PLL clock controller driver for the Amlogic T7 SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@xxxxxxxxxxx>
> ---
> drivers/clk/meson/Kconfig | 14 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/t7-pll.c | 1193 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 1208 insertions(+)
> create mode 100644 drivers/clk/meson/t7-pll.c
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 78f648c9c97d..6878b035a7ac 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -201,4 +201,18 @@ config COMMON_CLK_S4_PERIPHERALS
> help
> Support for the peripherals clock controller on Amlogic S805X2 and S905Y4
> devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.
> +
> +config COMMON_CLK_T7_PLL
> + tristate "Amlogic T7 SoC PLL controller support"
> + depends on ARM64
> + default y
> + select COMMON_CLK_MESON_REGMAP
> + select COMMON_CLK_MESON_CLKC_UTILS
> + select COMMON_CLK_MESON_PLL
> + imply COMMON_CLK_SCMI
> + help
> + Support for the PLL clock controller on Amlogic A311D2 based
> + device, AKA T7. PLLs are required by most peripheral to operate
> + Say Y if you are a T7 based device.
> +
> endmenu
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index bc56a47931c1..646257694c34 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
> obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
> obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
> +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
> diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c
> new file mode 100644
> index 000000000000..a6113b7dfe11
> --- /dev/null
> +++ b/drivers/clk/meson/t7-pll.c
> @@ -0,0 +1,1193 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> +/*
> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
> + * Author: Jian Hu <jian.hu@xxxxxxxxxxx>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include "clk-regmap.h"
> +#include "clk-pll.h"
> +#include "clk-mpll.h"
> +#include "meson-clkc-utils.h"
> +#include "meson-eeclk.h"
> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
> +
> +#define ANACTRL_GP0PLL_CTRL0 0x00
> +#define ANACTRL_GP0PLL_CTRL1 0x04
> +#define ANACTRL_GP0PLL_CTRL2 0x08
> +#define ANACTRL_GP0PLL_CTRL3 0x0c
> +#define ANACTRL_GP0PLL_CTRL4 0x10
> +#define ANACTRL_GP0PLL_CTRL5 0x14
> +#define ANACTRL_GP0PLL_CTRL6 0x18
> +#define ANACTRL_GP0PLL_STS 0x1c
> +
> +#define ANACTRL_GP1PLL_CTRL0 0x00
> +#define ANACTRL_GP1PLL_CTRL1 0x04
> +#define ANACTRL_GP1PLL_CTRL2 0x08
> +#define ANACTRL_GP1PLL_CTRL3 0x0c
> +#define ANACTRL_GP1PLL_STS 0x1c
> +
> +#define ANACTRL_HIFIPLL_CTRL0 0x00
> +#define ANACTRL_HIFIPLL_CTRL1 0x04
> +#define ANACTRL_HIFIPLL_CTRL2 0x08
> +#define ANACTRL_HIFIPLL_CTRL3 0x0c
> +#define ANACTRL_HIFIPLL_CTRL4 0x10
> +#define ANACTRL_HIFIPLL_CTRL5 0x14
> +#define ANACTRL_HIFIPLL_CTRL6 0x18
> +#define ANACTRL_HIFIPLL_STS 0x1c
> +
> +#define ANACTRL_PCIEPLL_CTRL0 0x00
> +#define ANACTRL_PCIEPLL_CTRL1 0x04
> +#define ANACTRL_PCIEPLL_CTRL2 0x08
> +#define ANACTRL_PCIEPLL_CTRL3 0x0c
> +#define ANACTRL_PCIEPLL_CTRL4 0x10
> +#define ANACTRL_PCIEPLL_CTRL5 0x14
> +#define ANACTRL_PCIEPLL_STS 0x18
> +
> +#define ANACTRL_MPLL_CTRL0 0x00
> +#define ANACTRL_MPLL_CTRL1 0x04
> +#define ANACTRL_MPLL_CTRL2 0x08
> +#define ANACTRL_MPLL_CTRL3 0x0c
> +#define ANACTRL_MPLL_CTRL4 0x10
> +#define ANACTRL_MPLL_CTRL5 0x14
> +#define ANACTRL_MPLL_CTRL6 0x18
> +#define ANACTRL_MPLL_CTRL7 0x1c
> +#define ANACTRL_MPLL_CTRL8 0x20
> +#define ANACTRL_MPLL_STS 0x24
> +
> +#define ANACTRL_HDMIPLL_CTRL0 0x00
> +#define ANACTRL_HDMIPLL_CTRL1 0x04
> +#define ANACTRL_HDMIPLL_CTRL2 0x08
> +#define ANACTRL_HDMIPLL_CTRL3 0x0c
> +#define ANACTRL_HDMIPLL_CTRL4 0x10
> +#define ANACTRL_HDMIPLL_CTRL5 0x14
> +#define ANACTRL_HDMIPLL_CTRL6 0x18
> +#define ANACTRL_HDMIPLL_STS 0x1c
> +
> +#define ANACTRL_MCLK_PLL_CNTL0 0x00
> +#define ANACTRL_MCLK_PLL_CNTL1 0x04
> +#define ANACTRL_MCLK_PLL_CNTL2 0x08
> +#define ANACTRL_MCLK_PLL_CNTL3 0x0c
> +#define ANACTRL_MCLK_PLL_CNTL4 0x10
> +#define ANACTRL_MCLK_PLL_STS 0x14
> +
> +static const struct pll_mult_range media_pll_mult_range = {
> + .min = 125,
> + .max = 250,
> +};
