> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> Sent: Friday, 10 January, 2025 8:57 PM
> To: Rabara, Niravkumar L <niravkumar.l.rabara@xxxxxxxxx>; Dinh Nguyen
> <dinguyen@xxxxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>; Krzysztof Kozlowski
> <krzk+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Cc: lkp <lkp@xxxxxxxxx>
> Subject: Re: [PATCH] arm64: dts: socfpga: stratix10_swvp: remove invalid sysmgr
> properties
>
> On 10/01/2025 13:39, Rabara, Niravkumar L wrote:
> >>> &sysmgr {
> >>> reg = <0xffd12000 0x1000>;
> >>> - interrupts = <0x0 0x10 0x4>;
> >>
> >> Is this correct? Some background would be useful.
> >
> > stratix10_swvp.dts is for legacy Stratix10 SW Virtual Platform.
> > The socfpga system manager dt binding does not include "interrupt"
> > property and the existing socfpga board files does not use it for sysmgr.
> > (e.g. Cyclon5/Arria10/stratix10/Agilex)
> >
> > Socfpga system manager drivers (altera-sysmgr.c/socfpga.c) also does
> > not use interrupt property.
> > The stratix10_swvp.dts has this property since beginning(unused) but
> > dtbs_check warning only appeared recently when I convert system manger
> > binding from txt to yaml.
> All this I deduced from the change, but it still not answer about hardware.
System Manager hardware block contains control and status registers for
some IPs like EMAC, FPGA to SOC bridge, ECC, USB etc.
e.g
For EMAC, to configure/check PHY interface selection for GMII/RGMII/RMII.
For ECC, interrupt mask and status register for USB, Onchip RAM, EMAC etc.
Scratch pad registers to pass handoff data from FPGA Secure device manager
to bootloader.
There is a global system manager interrupt(System Manger -> GIC -> CPU)
to serve single/double bit ECC interrupt to CPU.
Since its dedicated for ECC usage in HW it is not included in system manager
dt bindings instead it’s a part of ECC manager bindings.
Thanks,
Nirav
