Hi Jacky,
On 1/10/25 03:15, Jacky Chou wrote:
Hi Andrew,
Thank you for your reply.
I think the code already exist in the mainline:
https://github.com/torvalds/linux/blob/master/drivers/clk/clk-ast2600.
c#L595
It is configuring SCU register in the ast2600 SOC to introduce delays.
The mac is part of the SOC.
I could be reading this wrong, but that appears to create a gated clock.
hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
&aspeed_g6_clk_lock);
/**
* clk_hw_register_gate - register a gate clock with the clock framework
* @dev: device that is registering this clock
* @name: name of this clock
* @parent_name: name of this clock's parent
* @flags: framework-specific flags for this clock
* @reg: register address to control gating of this clock
* @bit_idx: which bit in the register controls gating of this clock
* @clk_gate_flags: gate-specific flags for this clock
* @lock: shared register lock for this clock */
There is nothing here about writing a value into @reg at creation time to give
it a default value. If you look at the vendor code, it has extra writes, but i don't
see anything like that in mainline.
Agree. You are right. This part is used to create a gated clock.
We will configure these RGMII delay in bootloader like U-boot.
Therefore, here does not configure delay again.
Currently, the delay of RGMII is configured in SCU region not in ftgma100 region.
And I studied ethernet-controller.yaml file, as you said, it has defined about rgmii
delay property for MAC side to set.
My plan is that I will move this delay setting to ftgmac100 driver from SCU.
Add a SCU syscon property for ftgmac100 driver configures the RGMII delay.
// aspeed-g6.dtsi
mac0: ethernet@1e660000 {
compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
aspeed,scu = <&syscon>; ------> add
status = "disabled";
};
Because AST2600 MAC1/2 RGMII delay setting in scu region is combined to one 32-bit register,
MAC3/4 is also. I will also use 'aliase' to get MAC index to set delay in scu.
// aspeed-g6.dtsi
aliases {
..........
mac0 = &mac0;
mac1 = &mac1;
mac2 = &mac2;
mac4 = &mac3;
};
Then, we can use rx-internal-delay-ps and tx-internal-delay-ps property to configure delay
In ftgmac100 driver.
Thanks. When are you planning to push this change? I might need to hold
on to mac changes until then.
Regards,
Ninad
If you have any questions, please let me know. Thank you.
Thanks,
Jacky
