Adds support for the MMC2 interface on the MT8365 EVK board.
It introduces a fixed regulator for the MMC2 VDD33 supply and configures
the MMC2 node with a 4-bit bus width, high-speed capabilities, UHS
modes, and appropriate power supplies. Enabled SDIO IRQ, wakeup source,
and kept power during suspend for wireless chip functionality.
Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 85 +++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 7d90112a7e27..309dc76322d4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -53,6 +53,15 @@ memory@40000000 {
reg = <0 0x40000000 0 0xc0000000>;
};
+ mmc2_vdd33: mmc2_vdd33-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc2_vdd33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 121 0>;
+ enable-active-high;
+ };
+
usb_otg_vbus: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "otg_vbus";
@@ -197,6 +206,28 @@ &mmc1 {
status = "okay";
};
+&mmc2 {
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ hs400-ds-delay = <0x12012>;
+ keep-power-in-suspend;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-0 = <&mmc2_default_pins>;
+ pinctrl-1 = <&mmc2_uhs_pins>;
+ pinctrl-names = "default", "state_uhs";
+ sd-uhs-sdr104;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ vmmc-supply = <&mmc2_vdd33>;
+ vqmmc-supply = <&mt6357_vcn18_reg>;
+ wakeup-source;
+ status = "okay";
+};
+
&mt6357_pmic {
interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
@@ -410,6 +441,60 @@ cmd-dat-pins {
};
};
+ mmc2_default_pins: mmc2-default-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK>;
+ drive-strength = <4>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0>,
+ <MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1>,
+ <MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2>,
+ <MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3>,
+ <MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD>;
+ input-enable;
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ sys-en-pins {
+ pinmux = <MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120>;
+ output-low;
+ };
+ };
+
+ mmc2_uhs_pins: mmc2-uhs-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0>,
+ <MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1>,
+ <MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2>,
+ <MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3>,
+ <MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ ds-pins {
+ pinmux = <MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ sys-en-pins {
+ pinmux = <MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120>;
+ output-high;
+ };
+ };
+
uart0_pins: uart0-pins {
pins {
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
---
base-commit: 9d89551994a430b50c4fffcb1e617a057fa76e20
change-id: 20250109-mmc2-support-96b3ea516186
Best regards,
--
Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
