Document the Qualcomm SC7180 System on a Chip (SoC). This SoC is made up of multiple devices that have their own bindings, therefore this binding is for a "bus" that is the SoC node. TODO: Document all child nodes. This is woefully incomplete but at least shows what is involved with describing an SoC node in dt schema. Cc: Rob Herring <robh@xxxxxxxxxx> Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx> Cc: Conor Dooley <conor+dt@xxxxxxxxxx> Cc: <devicetree@xxxxxxxxxxxxxxx> Cc: Bjorn Andersson <andersson@xxxxxxxxxx> Cc: Konrad Dybcio <konradybcio@xxxxxxxxxx> Cc: <linux-arm-msm@xxxxxxxxxxxxxxx> Signed-off-by: Stephen Boyd <swboyd@xxxxxxxxxxxx> --- .../bindings/bus/qcom,soc-sc7180.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/qcom,soc-sc7180.yaml diff --git a/Documentation/devicetree/bindings/bus/qcom,soc-sc7180.yaml b/Documentation/devicetree/bindings/bus/qcom,soc-sc7180.yaml new file mode 100644 index 000000000000..56f8b75ecdab --- /dev/null +++ b/Documentation/devicetree/bindings/bus/qcom,soc-sc7180.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/qcom,soc-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7180 SoC + +maintainers: + - Bjorn Andersson <andersson@xxxxxxxxxx> + - Konrad Dybcio <konradybcio@xxxxxxxxxx> + +description: + Qualcomm's SC7180 System on a Chip (SoC). + +properties: + compatible: + items: + - const: qcom,soc-sc7180 + - const: simple-bus + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + clock-controller@100000: + $ref: /schemas/clock/qcom,gcc-sc7180.yaml# + + watchdog@17c10000: + $ref: /schemas/watchdog/qcom-wdt.yaml# + +required: + - compatible + - '#address-cells' + - '#size-cells' + - clock-controller@100000 + - watchdog@17c10000 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,soc-sc7180", "simple-bus"; + + // TODO: Is it possible to ignore the details? + clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc_RPMH_CXO_CLK>, + <&rpmhcc_RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd_SC7180_CX>; + }; + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; + }; + }; + +... -- https://chromeos.dev
