On 3.01.2025 8:31 AM, Luo Jie wrote: > The CMN PLL clock controller supplies clocks to the hardware > blocks that together make up the Ethernet function on Qualcomm > IPQ SoCs and to GCC. The driver is initially supported for > IPQ9574 SoC. > > The CMN PLL clock controller expects a reference input clock > from the on-board Wi-Fi block acting as clock source. The input > reference clock needs to be configured to one of the supported > clock rates. > > The controller supplies a number of fixed-rate output clocks. > For the IPQ9574, there is one output clock of 353 MHZ to PPE > (Packet Process Engine) hardware block, three 50 MHZ output > clocks and an additional 25 MHZ output clock supplied to the > connected Ethernet devices. The PLL also supplies a 24 MHZ > clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25 > MHZ clock to PCS. > > Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx> > --- Acked-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> Konrad
