On 3.01.2025 8:31 AM, Luo Jie wrote: > The CMN PLL clock controller allows selection of an input clock rate > from a defined set of input clock rates. It in-turn supplies fixed > rate output clocks to the hardware blocks that provide the ethernet > functions such as PPE (Packet Process Engine) and connected switch or > PHY, and to GCC. > > The reference clock of CMN PLL is routed from XO to the CMN PLL through > the internal WiFi block. > .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL. > > The reference input clock from WiFi to CMN PLL is fully controlled by > the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ). > Based on this frequency, the divider in the internal Wi-Fi block is > automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to > ensure output clock to CMN PLL is 48 MHZ. > > Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> Konrad
