On 22.11.2024 3:03 AM, Ziyue Zhang wrote:
> Add configurations in devicetree for PCIe0, including registers, clocks,
> interrupts and phy setting sequence.
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 158 +++++++++++++++++++++++++++
> 1 file changed, 158 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 868808918fd2..c56cc30a59f3 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -678,6 +678,164 @@ rpmhpd_opp_turbo_l1: opp-9 {
> };
> };
>
> + pcie: pcie@1c08000 {
> + compatible = "qcom,pcie-qcs615";
> + reg = <0x0 0x01c08000 0x0 0x3000>,
> + <0x0 0x40000000 0x0 0xf1d>,
> + <0x0 0x40000f20 0x0 0xa8>,
> + <0x0 0x40001000 0x0 0x1000>,
> + <0x0 0x40100000 0x0 0x100000>,
> + <0x0 0x01c0b000 0x0 0x1000>;
> +
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config",
> + "mhi";
Please match the property order/style to x1e80100.dtsi
[...]
> +
> + interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
Use QCOM_ICC_TAG_ACTIVE_ONLY on the CPU path
[...]
> +
> + pcie_phy: phy@1c0e000 {
> + compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy";
> + reg = <0x0 0x01c0e000 0x0 0x1000>;
> +
> + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_CLK>,
> + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
> + <&gcc GCC_PCIE_0_PIPE_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "refgen",
> + "pipe";
> +
> + clock-output-names = "pcie_0_pipe_clk";
> + #clock-cells = <0>;
> +
> + #phy-cells = <0>;
> +
> + resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> + reset-names = "phy";
Please add the NOCSR reset too
Konrad
