On 23/12/2024 10:58, Shubhrajyoti Datta wrote: > Hi Krzysztof, > > On Sat, Nov 23, 2024 at 10:14 PM Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote: >> >> On Fri, Nov 22, 2024 at 03:36:23PM +0530, Shubhrajyoti Datta wrote: >>> Add device tree bindings for AMD Versal NET EDAC for DDR controller. >>> >>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> >>> --- >>> >> > .. >>> + >>> + amd,dwidth: >>> + description: >>> + DDR memory controller device width. >> >> Use existing properties. > I am not finding any existing properties could you help me with some pointers. Really? `git grep width` gives plenty of choices, depending on the meaning. I don't know what this property is about - your description is not helping. Either obvious or not correct, because memory controller cannot have a width. Like width in cm? inches? > >> >> >>> + enum: [16, 32] >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + >>> + amd,num-chans: >>> + description: >>> + Number of channels. >> >> Use existing properties, e.g. some of the DDR schemas describing memory. >> Look how other bindings describe actual chips. > > could you share any example. My search didnt return anything I don't believe you tried to search then... There are like 5 bindings describing some parts of memory bus to choose from. There are dedicated bindings for DDR memory - it's all there. Look how other bindings reference JEDEC DDR. Best regards, Krzysztof
