On Tue, Dec 17, 2024 at 09:25:22AM -0600, Rob Herring wrote:
> On Fri, Dec 13, 2024 at 06:32:48PM +0100, J. Neuschäfer wrote:
> > The Fairchild MM74HC595 and other compatible parts have a latch clock
> > input (also known as storage register clock input), which must be
> > clocked once in order to apply any value that was serially shifted in.
>
> That sounds like all the existing parts have the signal and it is
> required to operate? Or just needed to write settings, but not read GPIO
> input state for example?
These parts are output-only (so, "GPO"s, arguably).
The situation with the latch signal is weirder, as I found out in the
meantime: These parts don't have a chip-select built in, but the
rising-edge triggered latch clock can be reinterpreted as an active-low
chip-select, because that would also rise after the appropriate number
of bits has been shifted through the SPI bus.
_ _ _ _
shift clock ____| |_| |_..._| |_| |_________
latch clock * trigger
___ ________
chip select# |___________________|
So, I now think that no additional signal and no binding change is
actually needed, just perhaps an explanatory comment.
>
> If the new parts are usable without latch, then they should have a
> fallback compatible. If they aren't usable, then it should be 1 binding
> patch.
AFAICT, the new part (onnn,74hc595a) behaves the same at the existing
(fairchild,74hc595 and nxp,74lvc594), with regards to the latch signal,
so my two binding patches are independent of other.
In other words, this one can be dropped, but the other still stands.
Best regards
-- jn
