From: Chen Wang <unicorn_wang@xxxxxxxxxxx> Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode. SG2042 PCIe controller supports two ways to report MSI: Method A, the PICe controller implements an MSI interrupt controller inside, and connect to PLIC upward through one interrupt line. Provides memory-mapped msi address, and by programming the upper 32 bits of the address to zero, it can be compatible with old pcie devices that only support 32-bit msi address. Method B, the PICe controller connects to PLIC upward through an independent MSI controller "sophgo,sg2042-msi" on the SOC. The MSI controller provides multiple(up to 32) interrupt sources to PLIC. Compared with the first method, the advantage is that the interrupt source is expanded, but because for SG2042, the msi address provided by the MSI controller is fixed and only supports 64-bit address(> 2^32), it is not compatible with old pcie devices that only support 32-bit msi address. This patchset depends on another patchset for the SG2042 MSI controller[msi]. If you need to test the DTS part, you need to apply the corresponding patchset. Link: https://lore.kernel.org/linux-riscv/cover.1733726057.git.unicorn_wang@xxxxxxxxxxx/ [msi] Thanks, Chen --- Changes in v2: The patch series is based on v6.13-rc2. Fixed following issues as per comments from Rob Herring, Bjorn Helgaas, thanks. - Improve driver binding description - Define a new embeded object property msi to replace the "sophgo,internal-msi". - Rename "sophgo,link-id" to "sophgo,pcie-port" as per suggestion from Bjorn, and add more explanaion for this property. - Use msi-parent. - Improve driver code: - Improve coding style. - Fix a bug and make sure num_applied_vecs updated with the max value. - Use the MSI parent model. - Remove .cpu_addr_fixup. - Reorder Kconfig menu item to keep them in alphabetical order by vendor. Changes in v1: The patch series is based on v6.12-rc7. You can simply review or test the patches at the link [1]. Link: https://lore.kernel.org/linux-riscv/cover.1731303328.git.unicorn_wang@xxxxxxxxxxx/ [1] --- Chen Wang (5): dt-bindings: pci: Add Sophgo SG2042 PCIe host PCI: sg2042: Add Sophgo SG2042 PCIe driver dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible riscv: sophgo: dts: add pcie controllers for SG2042 riscv: sophgo: dts: enable pcie for PioneerBox .../devicetree/bindings/mfd/syscon.yaml | 2 + .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 141 +++++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 89 +++ drivers/pci/controller/cadence/Kconfig | 11 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pcie-sg2042.c | 534 ++++++++++++++++++ 7 files changed, 790 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4 -- 2.34.1
