The Agilex5 provides three Synopsys XGMAC ethernet cores, that can be
used to transmit and receive data at 10M/100M/1G/2.5G over ethernet
connections and enables support for Time Sensitive Networking (TSN)
applications.
Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 90 ++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 1162978329c1637aa0fd9a4adef16a9ae5017ac3..0035caef5af2774083885cf2d0d8a38ee8be9627 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -141,6 +141,96 @@ soc: soc@0 {
device_type = "soc";
interrupt-parent = <&intc>;
+ gmac0: ethernet@10810000 {
+ compatible = "altr,socfpga-stmmac-agilex5",
+ "altr,socfpga-stmmac-a10-s10",
+ "snps,dwxgmac-2.10",
+ "snps,dwxgmac";
+ reg = <0x10810000 0x3500>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ max-frame-size = <3800>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ rx-fifo-depth = <16384>;
+ tx-fifo-depth = <32768>;
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+ reset-names = "stmmaceth", "ahb";
+ clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ snps,axi-config = <&stmmac_axi_emac0_setup>;
+ altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+ status = "disabled";
+
+ stmmac_axi_emac0_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+ };
+
+ gmac1: ethernet@10820000 {
+ compatible = "altr,socfpga-stmmac-agilex5",
+ "altr,socfpga-stmmac-a10-s10",
+ "snps,dwxgmac-2.10",
+ "snps,dwxgmac";
+ reg = <0x10820000 0x3500>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ max-frame-size = <3800>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ rx-fifo-depth = <16384>;
+ tx-fifo-depth = <32768>;
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+ reset-names = "stmmaceth", "ahb";
+ clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ snps,axi-config = <&stmmac_axi_emac1_setup>;
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ status = "disabled";
+
+ stmmac_axi_emac1_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+ };
+
+ gmac2: ethernet@10830000 {
+ compatible = "altr,socfpga-stmmac-agilex5",
+ "altr,socfpga-stmmac-a10-s10",
+ "snps,dwxgmac-2.10",
+ "snps,dwxgmac";
+ reg = <0x10830000 0x3500>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ max-frame-size = <3800>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ rx-fifo-depth = <16384>;
+ tx-fifo-depth = <32768>;
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+ reset-names = "stmmaceth", "ahb";
+ clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ snps,axi-config = <&stmmac_axi_emac2_setup>;
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ status = "disabled";
+
+ stmmac_axi_emac2_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+ };
+
clkmgr: clock-controller@10d10000 {
compatible = "intel,agilex5-clkmgr";
reg = <0x10d10000 0x1000>;
--
2.46.0
