Hi Val,
Am Donnerstag, 5. Dezember 2024, 06:50:46 CET schrieb Val Packett:
> RK3066 does have two "CIF" video capture interface blocks, add their
> corresponding clock IDs so that they could be used.
>
> Signed-off-by: Val Packett <val@xxxxxxxxxxxx>
please split this into two patches
- addition of the clock-ids to the dt-binding header
- setting the clock-ids in the clock driver
Thanks
Heiko
> ---
> drivers/clk/rockchip/clk-rk3188.c | 4 ++--
> include/dt-bindings/clock/rk3188-cru-common.h | 2 ++
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
> index 684233e72105..81e94b338d0f 100644
> --- a/drivers/clk/rockchip/clk-rk3188.c
> +++ b/drivers/clk/rockchip/clk-rk3188.c
> @@ -344,7 +344,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
>
> GATE(0, "pclkin_cif0", "ext_cif0", 0,
> RK2928_CLKGATE_CON(3), 3, GFLAGS),
> - INVERTER(0, "pclk_cif0", "pclkin_cif0",
> + INVERTER(PCLK_CIF0, "pclk_cif0", "pclkin_cif0",
> RK2928_CLKSEL_CON(30), 8, IFLAGS),
>
> FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
> @@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
>
> GATE(0, "pclkin_cif1", "ext_cif1", 0,
> RK2928_CLKGATE_CON(3), 4, GFLAGS),
> - INVERTER(0, "pclk_cif1", "pclkin_cif1",
> + INVERTER(PCLK_CIF1, "pclk_cif1", "pclkin_cif1",
> RK2928_CLKSEL_CON(30), 12, IFLAGS),
>
> COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
> diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
> index 01e14ab252a7..dd988cc9d582 100644
> --- a/include/dt-bindings/clock/rk3188-cru-common.h
> +++ b/include/dt-bindings/clock/rk3188-cru-common.h
> @@ -103,6 +103,8 @@
> #define PCLK_PERI 351
> #define PCLK_DDRUPCTL 352
> #define PCLK_PUBL 353
> +#define PCLK_CIF0 354
> +#define PCLK_CIF1 355
>
> /* hclk gates */
> #define HCLK_SDMMC 448
>
