On Tue, Dec 03, 2024 at 11:31:12AM -0600, Andrew Davis wrote: > Add a pattern property for pcie-ctrl which can be part of this controller. > > Signed-off-by: Andrew Davis <afd@xxxxxx> > --- > .../bindings/soc/ti/ti,j721e-system-controller.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml > index 9ba9cb100ab30..ead0679b30e3f 100644 > --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml > +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml > @@ -74,6 +74,12 @@ patternProperties: > description: > This is the ICSSG control region. > > + "^pcie-ctrl@[0-9a-f]+$": > + type: object > + $ref: /schemas/mfd/syscon.yaml# > + description: > + This is the PCIe control region. This device (parent) is a syscon already. There is no sub-block representation, because what would be next? Third child with a node per each register? Best regards, Krzysztof
