The Adreno GPU Management Unit (GMU) can also vote for DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core scale the interconnect ddr path. While scaling the interconnect path was sufficient, newer GPUs like the A750 requires specific vote parameters and bandwidth to achieve full functionnality. In order to get the vote values to be used by the GPU Management Unit (GMU), we need to parse all the possible OPP Bandwidths and create a vote value to be send to the appropriate Bus Control Modules (BCMs) declared in the GPU info struct. The added dev_pm_opp_get_bw() is used in this case. The vote array will then be used to dynamically generate the GMU bw_table sent during the GMU power-up. Those entries will then be used by passing the appropriate bandwidth level when voting for a GPU frequency. This will make sure all resources are equally voted for a same OPP, whatever decision is done by the GMU, it will ensure all resources votes are synchronized. Depends on [1] to avoid crashing when getting OPP bandwidths. [1] https://lore.kernel.org/all/20241128-topic-opp-fix-assert-index-check-v1-0-cb8bd4c0370e@xxxxxxxxxx/ Ran full vulkan-cts-1.3.7.3-0-gd71a36db16d98313c431829432a136dbda692a08 with mesa 25.0.0+git3ecf2a0518 on: - QRD8550 - QRD8650 - HDK8650 Patchset is based on current msm-next including preemption support. Any feedback is welcome. Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> --- Changes in v3: - I didn't take Dmitry's review tags since I significantly changed the patches - Dropped applied OPP change - Dropped QUIRK/FEATURE addition/rename in favor of checking the a6xx_info->bcms pointer - Switch a6xx_info->bcms to a pointer, so it can be easy to share the table - Generate AB votes in advance, the voting was wrong in v2 we need to quantitiwe each bandwidth value - Do not vote via GMU is there's only the OFF vote because DT doesn't have the right properties - Added defines for the a6xx_gmu freqs tables to not have magic 16 and 4 values - Renamed gpu_bw_votes to gpu_ib_votes to match the downstream naming - Changed the parameters of a6xx_hfi_set_freq() to u32 to match the data type we pass - Drop "request for maximum bus bandwidth usage" and merge it in previous changes - Link to v2: https://lore.kernel.org/r/20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@xxxxxxxxxx Changes in v2: - opp: rename to dev_pm_opp_get_bw, fix commit message and kerneldoc - remove quirks that are features and move them to a dedicated .features bitfield - get icc bcm kerneldoc, and simplify/cleanup a6xx_gmu_rpmh_bw_votes_init() - no more copies of data - take calculations from icc-rpmh/bcm-voter - move into a single cleaner function - fix a6xx_gmu_set_freq() but not calling dev_pm_opp_set_opp() if !bw_index - also vote for maximum bus bandwidth usage (AB) - overall fix typos in commit messages - Link to v1: https://lore.kernel.org/r/20241113-topic-sm8x50-gpu-bw-vote-v1-0-3b8d39737a9b@xxxxxxxxxx --- Neil Armstrong (7): drm/msm: adreno: add defines for gpu & gmu frequency table sizes drm/msm: adreno: add plumbing to generate bandwidth vote table for GMU drm/msm: adreno: dynamically generate GMU bw table drm/msm: adreno: find bandwidth index of OPP and set it along freq index drm/msm: adreno: enable GMU bandwidth for A740 and A750 arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU arm64: qcom: dts: sm8650: add interconnect and opp-peak-kBps for GPU arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 ++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++ drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 22 ++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 197 +++++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 27 +++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 45 ++++++- drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 5 + 8 files changed, 309 insertions(+), 13 deletions(-) --- base-commit: 18ac96e1bd761af2b7c2fc99901e9a813a6f3bb3 change-id: 20241113-topic-sm8x50-gpu-bw-vote-f5e022fe7a47 Best regards, -- Neil Armstrong <neil.armstrong@xxxxxxxxxx>
