Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P
SoCs.
Update the generic compatible for SM8250 and SC7280 SoCs to
"qcom,epss-l3-perf" as they use PERF_STATE register for L3 scaling.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 9f315a51a7c1..0c2bd15f9ef0 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
@@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 {
};
};
+ epss_l3_cl0: interconnect@18590000 {
+ compatible = "qcom,sm8250-epss-l3",
+ "qcom,epss-l3-perf";
+ reg = <0x0 0x18590000 0x0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sa8775p-cpufreq-epss",
"qcom,cpufreq-epss";
@@ -4295,6 +4305,15 @@ cpufreq_hw: cpufreq@18591000 {
#freq-domain-cells = <1>;
};
+ epss_l3_cl1: interconnect@18592000 {
+ compatible = "qcom,sm8250-epss-l3",
+ "qcom,epss-l3-perf";
+ reg = <0x0 0x18592000 0x0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
remoteproc_gpdsp0: remoteproc@20c00000 {
compatible = "qcom,sa8775p-gpdsp0-pas";
reg = <0x0 0x20c00000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 55db1c83ef55..544c6d725764 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -6125,7 +6125,7 @@ rpmhcc: clock-controller {
};
epss_l3: interconnect@18590000 {
- compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
+ compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3-perf";
reg = <0 0x18590000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 48318ed1ce98..f4a223bfe748 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -6230,7 +6230,7 @@ apps_bcm_voter: bcm-voter {
};
epss_l3: interconnect@18590000 {
- compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
+ compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3-perf";
reg = <0 0x18590000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
--
2.39.2
