On November 25, 2024 4:28:00 PM GMT+01:00, Maxime Ripard <mripard@xxxxxxxxxx> wrote: >On Mon, Nov 25, 2024 at 11:24:25PM +0900, Hector Martin wrote: >> >> >> On 2024/11/25 20:24, Sasha Finkelstein wrote: >> > On Mon, 25 Nov 2024 at 09:50, Neil Armstrong <neil.armstrong@xxxxxxxxxx> wrote: >> >> >> >> So this controller only supports a single mode ??????? >> >> >> > Most likely. On all devices it is connected to a single built-in display. >> >> More specifically, the controller obviously supports multiple modes but >> it is pre-initialized by the bootloader for the single hardwired >> display's only mode. So as far as the driver is concerned, there is a >> single possible mode, and there's no point in trying to be more generic >> if there is no hardware that would use that. > >It's not only about being generic, it's also about fitting nicely in the >usual abstractions. You could also always register a single panel, with >a single timing set, and the driver would never see anything else. And >still fall within the usual pattern. > >> In general, it is not possible/practical to be generic for reverse >> engineered hardware with no specs documenting how to drive it >> generically. You just can't know how to implement the options that are >> never used in practice. I spent a lot of time on exceptions to this >> rule for the GPIO and SPI controllers, and that's not going to happen >> for more complex hardware like MIPI DSI. > >How is GPIO or SPI even remotely related to that discussion? We are >different maintainers, with different concerns, and different things to >care about. > >Also, "My way or the highway" is never a great discussion opener. This was not an attempt to push back on the review feedback at all. I was just trying to add context about *why* the controller will never be used with nor support more than a single mode, not argue about how that should be implemented. Sorry if it came across as otherwise. GPIO and SPI are relevant not because of anything related to the kernel, but because I was able to reverse engineer the generic features of those controllers quite comprehensively by literally probing a GPIO routed to an external USB-C port with a custom test bench and an oscilloscope (for GPIO) and by using the GPIO registers along with a bespoke bare-metal test platform as a "software" logic analyzer to inspect the signals generated as I twiddled register bits (for SPI). I'd love to have all hardware comprehensively documented like that (I did GPIO and SPI because I wanted to, not because any maintainer asked for it), but as you might imagine, this kind of deep hardware RE doesn't scale and isn't practical for anything more complex, and I was just trying to convey that fact. (Sending from mobile, apologies for the likely dodgy line wrap) -- Hector
