On 25/11/2024 11:33, Steffen Trumtrar wrote:
> The Agilex5 provides three Synopsys XGMAC ethernet cores, that can be
> used to transmit and receive data at 10M/100M/1G/2.5G over ethernet
> connections and enables support for Time Sensitive Networking (TSN)
> applications.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 87 ++++++++++++++++++++++++++
> 1 file changed, 87 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index b1debf0317d0576f7b00200e9593481671183faa..647ccd0b5a66b68fab745d443b975c12d6ce63df 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -141,6 +141,93 @@ soc: soc@0 {
> device_type = "soc";
> interrupt-parent = <&intc>;
>
> + gmac0: ethernet@10810000 {
> + compatible = "altr,socfpga-stmmac-a10-s10",
That's odd compatible, this is not Arria10 SoC, neither Stratix 10.
Best regards,
Krzysztof
