On 13/11/2024 13:09, MD Danish Anwar wrote: > ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG > nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at > 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at > 333MHz. > > ICSSG_CORE clock will help get the most out of ICSSG as more cycles are > needed to fully support all ICSSG features. > > This commit also changes assigned-clock-parents of coreclk-mux to > ICSSG_CORE clock from ICSSG_ICLK. > > Performance update in dual mac mode > With ICSSG_CORE Clk @ 333MHz > Tx throughput - 934 Mbps > Rx throughput - 914 Mbps, > > With ICSSG_ICLK clk @ 250MHz, > Tx throughput - 920 Mbps > Rx throughput - 706 Mbps > > Signed-off-by: MD Danish Anwar <danishanwar@xxxxxx> It would be nice if you could send patches to update corresponding nodes in am65 and j721e platforms as well else we will start getting dtbs_check errors. Reviewed-by: Roger Quadros <rogerq@xxxxxxxxxx>
