The patchset adds support for the peripheral and PLL clock controller found on the Amlogic A5 SoC family, such as A113X2. Some clocks are provided by security zones. These clock accessed througth SCMI driver in linux, inlcuding OSC, SYS_CLK, AXI_CLK, CPU_CLK, DSU_CLK, GP1_PLL, FIXED_PLL_DCO, FIXED_PLL, SYS_PLL_DIV16, ACLKM, CPU_CLK_DIV16, FCLK_50M_PREDIV, FCLK_50M_DIV, FCLK_50M, FCLK_DIV2_DIV, FCLK_DIV2, FCLK_DIV2P5_DIV, FCLK_DIV2P5, FCLK_DIV3_DIV, FCLK_DIV3, FCLK_DIV4_DIV, FCLK_DIV4, FCLK_DIV5_DIV, FCLK_DIV5, FCLK_DIV7_DIV, FCLK_DIV7, CLKID_SYS_MMC_PCLK, CLKID_SYS_CPU_CTRL, CLKID_SYS_IRQ_CTRL, CLKID_SYS_GIC, CLKID_SYS_BIG_NIC, CLKID_AXI_SYS_NIC, and CLKID_AXI_CPU_DMC. Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx> --- Changes in v2: - Move some sys clock and axi clock from peripheral to scmi impletement. - Remove ARM_SCMI_PROTOCOL in Kconfig and correct name A5 but not A4. - Add two optional clock inputs for the peripheral(ddr pll and clk-measure) - Make some changes and adjustments according to suggestions. - Link to v1: https://lore.kernel.org/r/20240914-a5-clk-v1-0-5ee2c4f1b08c@xxxxxxxxxxx --- Chuan Liu (5): dt-bindings: clock: add Amlogic A5 PLL clock controller dt-bindings: clock: add Amlogic A5 SCMI clock controller support dt-bindings: clock: add Amlogic A5 peripherals clock controller clk: meson: add support for the A5 SoC PLL clock clk: meson: add A5 clock peripherals controller driver .../clock/amlogic,a5-peripherals-clkc.yaml | 130 ++ .../bindings/clock/amlogic,a5-pll-clkc.yaml | 62 + drivers/clk/meson/Kconfig | 27 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/a5-peripherals.c | 1387 ++++++++++++++++++++ drivers/clk/meson/a5-pll.c | 543 ++++++++ drivers/clk/meson/clk-regmap.h | 17 + .../clock/amlogic,a5-peripherals-clkc.h | 132 ++ include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 + include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 + 10 files changed, 2368 insertions(+) --- base-commit: 961101258aa2da34b032ea21f32599a895448996 change-id: 20240911-a5-clk-35c49acb34e1 Best regards, -- Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
