On Tue, Nov 19, 2024 at 04:00:19PM +0100, Jan Petrous (OSS) wrote: > Add basic description for DWMAC ethernet IP on NXP S32G2xx, S32G3xx > and S32R45 automotive series SoCs. > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@xxxxxxxxxxx> > --- > .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 105 +++++++++++++++++++++ > .../devicetree/bindings/net/snps,dwmac.yaml | 3 + > 2 files changed, 108 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml > new file mode 100644 > index 000000000000..a141e826a295 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2021-2024 NXP > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller > + > +maintainers: > + - Jan Petrous (OSS) <jan.petrous@xxxxxxxxxxx> > + > +description: > + This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs. > + The SoC series S32G2xx and S32G3xx feature one DWMAC instance, > + the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII > + interface over Pinctrl device or the output can be routed > + to the embedded SerDes for SGMII connectivity. > + > +properties: > + compatible: > + oneOf: > + - const: nxp,s32g2-dwmac > + - items: > + - enum: > + - nxp,s32g3-dwmac > + - nxp,s32r45-dwmac > + - const: nxp,s32g2-dwmac > + > + reg: > + items: > + - description: Main GMAC registers > + - description: GMAC PHY mode control register > + > + interrupts: > + maxItems: 1 > + > + interrupt-names: > + const: macirq > + > + clocks: > + items: > + - description: Main GMAC clock > + - description: Transmit clock > + - description: Receive clock > + - description: PTP reference clock > + > + clock-names: > + items: > + - const: stmmaceth > + - const: tx > + - const: rx > + - const: ptp_ref > + > +required: > + - clocks > + - clock-names > + > +allOf: > + - $ref: snps,dwmac.yaml# > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/phy/phy.h> > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + ethernet@4033c000 { > + compatible = "nxp,s32g2-dwmac"; > + reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ > + <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq"; > + snps,mtl-rx-config = <&mtl_rx_setup>; > + snps,mtl-tx-config = <&mtl_tx_setup>; > + clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; > + clock-names = "stmmaceth", "tx", "rx", "ptp_ref"; > + phy-mode = "rgmii-id"; > + phy-handle = <&phy0>; > + > + mtl_rx_setup: rx-queues-config { > + snps,rx-queues-to-use = <5>; > + }; > + > + mtl_tx_setup: tx-queues-config { > + snps,tx-queues-to-use = <5>; > + }; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + > + phy0: ethernet-phy@0 { > + reg = <0>; > + }; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > index 4e2ba1bf788c..a88d1c236eaf 100644 > --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml > +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > @@ -66,6 +66,9 @@ properties: > - ingenic,x2000-mac > - loongson,ls2k-dwmac > - loongson,ls7a-dwmac > + - nxp,s32g2-dwmac > + - nxp,s32g3-dwmac > + - nxp,s32r-dwmac You really only need to add nxp,s32g2-dwmac since it's always present. Other than the yamllint issue, Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
