On 11/12/24 19:28, Bjorn Helgaas wrote:
On Tue, Nov 12, 2024 at 05:19:21PM +0100, Christian Bruel wrote:
Document the bindings for STM32MP25 PCIe Controller configured in
root complex mode.
Supports 4 legacy interrupts and MSI interrupts from the ARM
GICv2m controller.
Allow tuning to change payload (default 128B) thanks to the
st,max-payload-size entry.
Can also limit the Maximum Read Request Size on downstream devices to the
minimum possible value between 128B and 256B.
STM32 PCIE may be in a power domain which is the case for the STM32MP25
based boards.
Supports wake# from wake-gpios
+ st,limit-mrrs:
+ description: If present limit downstream MRRS to 256B
+ type: boolean
+
+ st,max-payload-size:
+ description: Maximum Payload size to use
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [128, 256]
+ default: 128
MRRS and MPS are not specific to this device. Not sure why you need
them, but if you do need them, I think they should be generic.
Agree. On a second thought, this was to fix an old errata and can be
dropped now, as well as the associated quirks.
Will re-post as generic if needed later on
thanks,
Christian
