Quoting Nuno Sa (2024-10-29 06:59:42)
> In order to access the registers of the HW, we need to make sure that
> the AXI bus clock is enabled. Hence let's increase the number of clocks
> by one.
>
> In order to keep backward compatibility and make sure old DTs still work
> we check if clock-names is available or not. If it is, then we can
> disambiguate between really having the AXI clock or a parent clock and
> so we can enable the bus clock. If not, we fallback to what was done
> before and don't explicitly enable the AXI bus clock.
>
> Note that if clock-names is given, the axi clock must be the last one in
> the phandle array (also enforced in the DT bindings) so that we can reuse
> as much code as possible.
>
> Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver")
> Signed-off-by: Nuno Sa <nuno.sa@xxxxxxxxxx>
> ---
Applied to clk-next
