STM32MP25 PCIe Controller is based on the DesignWare core configured as end point mode from the SYSCFG register. Signed-off-by: Christian Bruel <christian.bruel@xxxxxxxxxxx> --- .../bindings/pci/st,stm32-pcie-ep.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml new file mode 100644 index 000000000000..f0d215982794 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP25 PCIe endpoint driver + +maintainers: + - Christian Bruel <christian.bruel@xxxxxxxxxxx> + +description: + PCIe endpoint controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: addr_space + + clocks: + maxItems: 1 + description: PCIe system clock + + clock-names: + const: core + + resets: + maxItems: 1 + + reset-names: + const: core + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + access-controllers: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - resets + - reset-names + - clocks + - clock-names + - phys + - phy-names + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/st,stm32mp25-rcc.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/reset/st,stm32mp25-rcc.h> + + pcie-ep@48400000 { + compatible = "st,stm32mp25-pcie-ep"; + num-lanes = <1>; + reg = <0x48400000 0x400000>, + <0x10000000 0x8000000>; + reg-names = "dbi", "addr_space"; + clocks = <&rcc CK_BUS_PCIE>; + clock-names = "core"; + phys = <&combophy PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + resets = <&rcc PCIE_R>; + reset-names = "core"; + pinctrl-names = "default", "init"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + power-domains = <&CLUSTER_PD>; + access-controllers = <&rifsc 68>; + }; -- 2.34.1
