On 10/18/2024 4:22 AM, Konrad Dybcio wrote:
> On 17.10.2024 11:28 AM, Jagadeesh Kona wrote:
>> Add support to scale DDR and L3 based on CPU frequencies
>> on SA8775P platform.
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@xxxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 33 +++++++++++++++++++++++++++++++++
>> 1 file changed, 33 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 06bf2ba556b89b643da901857a9aa7cdc7ba90cc..d8b90bd4b1f05604185f015929a1f296799ad6a4 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -4,6 +4,7 @@
>> */
>>
>> #include <dt-bindings/interconnect/qcom,icc.h>
>> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
>> @@ -47,6 +48,10 @@ CPU0: cpu@0 {
>> next-level-cache = <&L2_0>;
>> capacity-dmips-mhz = <1024>;
>> dynamic-power-coefficient = <100>;
>> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
>
> Please align the '&'s and squash with patch 2. This one doesn't cause
> much difference on its own, which makes the commit message misleading
>
> Konrad
Thanks Konrad for your review. Sure will take care of this in next series.
Thanks,
Jagadeesh
