Add support to scale DDR and L3 based on CPU frequencies
on SA8775P platform.
Signed-off-by: Jagadeesh Kona <quic_jkona@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 06bf2ba556b89b643da901857a9aa7cdc7ba90cc..d8b90bd4b1f05604185f015929a1f296799ad6a4 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
@@ -47,6 +48,10 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -69,6 +74,10 @@ CPU1: cpu@100 {
next-level-cache = <&L2_1>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -86,6 +95,10 @@ CPU2: cpu@200 {
next-level-cache = <&L2_2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
L2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -103,6 +116,10 @@ CPU3: cpu@300 {
next-level-cache = <&L2_3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl0 MASTER_EPSS_L3_APPS
+ &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
L2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -120,6 +137,10 @@ CPU4: cpu@10000 {
next-level-cache = <&L2_4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
L2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -143,6 +164,10 @@ CPU5: cpu@10100 {
next-level-cache = <&L2_5>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
L2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -160,6 +185,10 @@ CPU6: cpu@10200 {
next-level-cache = <&L2_6>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
L2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -177,6 +206,10 @@ CPU7: cpu@10300 {
next-level-cache = <&L2_7>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3_cl1 MASTER_EPSS_L3_APPS
+ &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
L2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
--
2.34.1
