Cheers,
Biju
>
> Thank you,
> Claudiu Beznea
>
> >
> > Maybe add audio_clk1, so that it described properly in clock tree??
> >
> > Cheers,
> > Biju
> >
> >> +&audio_clk2 {
> >> + clock-frequency = <12288000>;
> >> + status = "okay";
> >> +};
> >> +
> >> &i2c0 {
> >> status = "okay";
> >>
> >> @@ -94,6 +99,11 @@ da7212: codec@1a { };
> >>
> >> &pinctrl {
> >> + audio_clock_pins: audio-clock {
> >> + pins = "AUDIO_CLK1", "AUDIO_CLK2";
> >> + input-enable;
> >> + };
> >> +
> >> key-1-gpio-hog {
> >> gpio-hog;
> >> gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>; @@ -151,6 +161,13 @@ cd {
> >> pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
> >> };
> >> };
> >> +
> >> + ssi3_pins: ssi3 {
> >> + pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
> >> + <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
> >> + <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
> >> + <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
> >> + };
> >> };
> >>
> >> &scif0 {
> >> @@ -171,3 +188,12 @@ &sdhi1 {
> >> max-frequency = <125000000>;
> >> status = "okay";
> >> };
> >> +
> >> +&ssi3 {
> >> + clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
> >> + <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
> >> + <&versa3 2>, <&audio_clk2>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
> >> + status = "okay";
> >> +};
> >> --
> >> 2.39.2
> >
