On Fri, Nov 08, 2024 at 03:04:29PM +0100, Alexander Stein wrote:
> Hi,
>
> Am Freitag, 8. November 2024, 10:56:46 CET schrieb Pengfei Li:
> > On Thu, Nov 07, 2024 at 01:49:50PM +0100, Alexander Stein wrote:
> > > Hi,
> > >
> > > thanks for putting me on CC.
> > >
> > > Am Freitag, 8. November 2024, 03:27:02 CET schrieb Pengfei Li:
> > > > The i.MX 91 family features an Arm Cortex-A55 running at up to
> > > > 1.4GHz, support for modern LPDDR4 memory to enable platform longevity,
> > > > along with a rich set of peripherals targeting medical, industrial
> > > > and consumer IoT market segments.
> > > >
> > > > The design of the i.MX91 platform is very similar to i.MX93.
> > > > The mainly difference between i.MX91 and i.MX93 is as follows:
> > > > - i.MX91 removed some clocks and modified the names of some clocks.
> > > > - i.MX91 only has one A core
> > > >
> > > > Signed-off-by: Pengfei Li <pengfei.li_1@xxxxxxx>
> > > > Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/imx91-pinfunc.h | 770 ++++++++++++++++++
> > > > arch/arm64/boot/dts/freescale/imx91.dtsi | 66 ++
> > > > 2 files changed, 836 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/freescale/imx91-pinfunc.h
> > > > create mode 100644 arch/arm64/boot/dts/freescale/imx91.dtsi
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx91-pinfunc.h b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h
> > > > new file mode 100644
> > > > index 000000000000..bc58ce2102b2
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h
> > >
> > > FWIW this is a 1:1 copy from downstream kernel
> >
> > Hi, thanks for the comments.
> >
> > Yes, it is same as downstream kernel.
> >
> > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi
> > > > new file mode 100644
> > > > index 000000000000..a9f4c1fe61cc
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi
> > > > @@ -0,0 +1,66 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + * Copyright 2024 NXP
> > > > + */
> > > > +
> > > > +#include "imx91-pinfunc.h"
> > > > +#include "imx93.dtsi"
> > > > +
> > > > +&{/thermal-zones/cpu-thermal/cooling-maps/map0} {
> > > > + cooling-device =
> > > > + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > > > +};
> > > > +
> > > > +&clk {
> > > > + compatible = "fsl,imx91-ccm";
> > > > +};
> > > > +
> > > > +&eqos {
> > > > + clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
> > > > + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
> > > > + <&clk IMX91_CLK_ENET_TIMER>,
> > > > + <&clk IMX91_CLK_ENET1_QOS_TSN>,
> > > > + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
> > > > + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
> > > > + <&clk IMX91_CLK_ENET1_QOS_TSN>;
> > > > + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> > > > + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
> > >
> > > Is it just me or is the alignment of new lines not matching?
> >
> > Not sure about others, the alignment on my side is correct.
> >
> > >
> > >
> > > > +};
> > > > +
> > > > +&fec {
> > > > + clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
> > > > + <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
> > > > + <&clk IMX91_CLK_ENET_TIMER>,
> > > > + <&clk IMX91_CLK_ENET2_REGULAR>,
> > > > + <&clk IMX93_CLK_DUMMY>;
> > > > + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
> > > > + <&clk IMX91_CLK_ENET2_REGULAR>;
> > > > + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> > > > + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
> > >
> > > Here as well: Is it just me or is the alignment of new lines not matching?
> >
> > Same as above.
> >
> > >
> > > > + assigned-clock-rates = <100000000>, <250000000>;
> > > > +};
> > > > +
> > > > +&i3c1 {
> > > > + clocks = <&clk IMX93_CLK_BUS_AON>,
> > > > + <&clk IMX93_CLK_I3C1_GATE>,
> > > > + <&clk IMX93_CLK_DUMMY>;
> > > > +};
> > > > +
> > > > +&i3c2 {
> > > > + clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
> > > > + <&clk IMX93_CLK_I3C2_GATE>,
> > > > + <&clk IMX93_CLK_DUMMY>;
> > > > +};
> > > > +
> > > > +&tmu {
> > > > + status = "disabled";
> > >
> > > Why does the TMU needs to be disabled instead of deleted?
> >
> > Actually, the i.MX91 also has a TMU, but the i.MX91 uses a different IP than the i.MX93, so a new driver is required.
> > However, this new driver is not applied yet on upstream kernel, so it is disabled here for now.
>
> Then, the compatible should be changed as well.
Ok, the new tmu driver and dt bindings and the compatible changes for this node will be included in the subsequent tmu patch set.
BR,
Pengfei Li
