From: Heiko Stuebner <heiko.stuebner@xxxxxxxxx>
Add the two MIPI-DC-phy nodes to the RK3588, that will be used by the
DSI2 controllers and hopefully in some future also for camera input.
Signed-off-by: Heiko Stuebner <heiko.stuebner@xxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 51ba7563f7d0..8c95c56e8097 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -576,6 +576,16 @@ sys_grf: syscon@fd58c000 {
reg = <0x0 0xfd58c000 0x0 0x1000>;
};
+ mipidcphy0_grf: syscon@fd5e8000 {
+ compatible = "rockchip,rk3588-dcphy-grf", "syscon";
+ reg = <0x0 0xfd5e8000 0x0 0x4000>;
+ };
+
+ mipidcphy1_grf: syscon@fd5ec000 {
+ compatible = "rockchip,rk3588-dcphy-grf", "syscon";
+ reg = <0x0 0xfd5ec000 0x0 0x4000>;
+ };
+
vop_grf: syscon@fd5a4000 {
compatible = "rockchip,rk3588-vop-grf", "syscon";
reg = <0x0 0xfd5a4000 0x0 0x2000>;
@@ -2878,6 +2888,38 @@ usbdp_phy0: phy@fed80000 {
status = "disabled";
};
+ mipidcphy0: phy@feda0000 {
+ compatible = "rockchip,rk3588-mipi-dcphy";
+ reg = <0x0 0xfeda0000 0x0 0x10000>;
+ rockchip,grf = <&mipidcphy0_grf>;
+ clocks = <&cru PCLK_MIPI_DCPHY0>,
+ <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
+ clock-names = "pclk", "ref";
+ resets = <&cru SRST_M_MIPI_DCPHY0>,
+ <&cru SRST_P_MIPI_DCPHY0>,
+ <&cru SRST_P_MIPI_DCPHY0_GRF>,
+ <&cru SRST_S_MIPI_DCPHY0>;
+ reset-names = "m_phy", "apb", "grf", "s_phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipidcphy1: phy@fedb0000 {
+ compatible = "rockchip,rk3588-mipi-dcphy";
+ reg = <0x0 0xfedb0000 0x0 0x10000>;
+ rockchip,grf = <&mipidcphy1_grf>;
+ clocks = <&cru PCLK_MIPI_DCPHY1>,
+ <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
+ clock-names = "pclk", "ref";
+ resets = <&cru SRST_M_MIPI_DCPHY1>,
+ <&cru SRST_P_MIPI_DCPHY1>,
+ <&cru SRST_P_MIPI_DCPHY1_GRF>,
+ <&cru SRST_S_MIPI_DCPHY1>;
+ reset-names = "m_phy", "apb", "grf", "s_phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
--
2.45.2
