On Mon, 28 Oct 2024 22:45:34 +0100 Angelo Dureghello <angelo@xxxxxxxxxxxxxxxx> wrote: > From: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > > Add High Speed ad3552r platform driver. > > The ad3552r DAC is controlled by a custom (fpga-based) DAC IP > through the current AXI backend, or similar alternative IIO backend. > > Compared to the existing driver (ad3552r.c), that is a simple SPI > driver, this driver is coupled with a DAC IIO backend that finally > controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach > maximum transfer rate of 33MUPS using dma stream capabilities. > > All commands involving QSPI bus read/write are delegated to the backend > through the provided APIs for bus read/write. > > Reviewed-by: Nuno Sa <nuno.sa@xxxxxxxxxx> > Signed-off-by: Angelo Dureghello <adureghello@xxxxxxxxxxxx> Missing bitfield.h include. I added whilst applying. Jonathan
