Re: [PATCH v5 4/4] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC

[Jie Luo <quic_luoj@xxxxxxxxxxx>]

On 10/28/2024 11:39 PM, Dmitry Baryshkov wrote:
> On Mon, Oct 28, 2024 at 10:04:11PM +0800, Luo Jie wrote:
> > The CMN PLL clock controller allows selection of an input clock rate
> > from a defined set of input clock rates. It in-turn supplies fixed
> > rate output clocks to the hardware blocks that provide the ethernet
> > functions such as PPE (Packet Process Engine) and connected switch or
> > PHY, and to GCC.
> >
> > The reference clock of CMN PLL is routed from XO to the CMN PLL through
> > the internal WiFi block.
> > .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL.
> >
> > The reference input clock from WiFi to CMN PLL is fully controlled by
> > the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ).
> > Based on this frequency, the divider in the internal Wi-Fi block is
> > automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to
> > ensure output clock to CMN PLL is 48 MHZ.
> >
> > Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 16 ++++++++++++++-
> >   arch/arm64/boot/dts/qcom/ipq9574.dtsi            | 26 +++++++++++++++++++++++-
> >   2 files changed, 40 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> > index 91e104b0f865..f026c2a9d0c0 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> > @@ -3,7 +3,7 @@
> >    * IPQ9574 RDP board common device tree source
> >    *
> >    * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> > - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> > + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
> >    */
> >   
> >   /dts-v1/;
> > @@ -164,6 +164,20 @@ &usb3 {
> >   	status = "okay";
> >   };
> >   
> > +/*
> > + * The bootstrap pins for the board select the XO clock frequency,
> > + * which automatically enables the right dividers to ensure the
> > + * reference clock output to CMNPLL is 48 MHZ.
> > + */
> > +&cmn_pll_ref_clk {
> > +	clock-div = <1>;
> > +	clock-mult = <1>;
> > +};
> > +
> >   &xo_board_clk {
> >   	clock-frequency = <24000000>;
> >   };
> > +
> > +&xo_clk {
> > +	clock-frequency = <48000000>;
> > +};
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > index 14c7b3a78442..ad9cdb1f76db 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > @@ -3,10 +3,11 @@
> >    * IPQ9574 SoC device tree source
> >    *
> >    * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> > - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> > + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
> >    */
> >   
> >   #include <dt-bindings/clock/qcom,apss-ipq.h>
> > +#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
> >   #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> >   #include <dt-bindings/interconnect/qcom,ipq9574.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -19,6 +20,12 @@ / {
> >   	#size-cells = <2>;
> >   
> >   	clocks {
> > +		cmn_pll_ref_clk: cmn-pll-ref-clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&xo_clk>;
> > +			#clock-cells = <0>;
> > +		};
> > +
> >   		sleep_clk: sleep-clk {
> >   			compatible = "fixed-clock";
> >   			#clock-cells = <0>;
> > @@ -28,6 +35,11 @@ xo_board_clk: xo-board-clk {
> >   			compatible = "fixed-clock";
> >   			#clock-cells = <0>;
> >   		};
> > +
> > +		xo_clk: xo-clk {
> > +			compatible = "fixed-clock";
> > +			#clock-cells = <0>;
> > +		};
>
> What is the difference between xo_clk and xo_board_clk? Are there two
> different crystals?

The xo_board_clk of 24 MHZ is generated by applying another divider in
HW (by 2), on top of the same 48 MHZ clock output from internal Wi-Fi.

XO (48 MHZ or 96 MHZ)-->WiFi (mul/div)-->48 MHZ-->fixed factor divider 2 
by HW ---> xo_board_clk (24 MHZ)

We may need to correct its clock chain representation. We will update
xo_board_clk as a fixed factor (div by 2) clock, and refer to the 48 MHZ
input clock, using a separate patch after the CMN PLL patch series
review is concluded. Hope this approach is fine.

> >   	};
> >   
> >   	cpus {