On Mon, Oct 28, 2024 at 09:24:55PM +0100, Jan Petrous (OSS) wrote: > Add basic description for DWMAC ethernet IP on NXP S32G2xx, S32G3xx > and S32R45 automotive series SoCs. > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@xxxxxxxxxxx> > --- > .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 98 ++++++++++++++++++++++ > .../devicetree/bindings/net/snps,dwmac.yaml | 3 + > 2 files changed, 101 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml > new file mode 100644 > index 000000000000..b11ba3bc4c52 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml > @@ -0,0 +1,98 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2021-2024 NXP > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller > + > +maintainers: > + - Jan Petrous (OSS) <jan.petrous@xxxxxxxxxxx> > + > +description: > + This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs. > + > +properties: > + compatible: > + enum: > + - nxp,s32g2-dwmac > + - nxp,s32g3-dwmac > + - nxp,s32r-dwmac Your driver says these are fully compatible, why this is not expressed here? > + > + reg: > + items: > + - description: Main GMAC registers > + - description: GMAC PHY mode control register > ... > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + > + phy0: ethernet-phy@0 { > + reg = <0>; Messed indentation. Keep it consistent. Best regards, Krzysztof
