On 10/22/2024 12:33 AM, Rob Herring wrote:
On Fri, Oct 18, 2024 at 02:22:45PM -0400, Jim Quinlan wrote:
Support configuration of the GEN3 preset equalization settings, aka the
Lane Equalization Control Register(s) of the Secondary PCI Express
Extended Capability. These registers are of type HwInit/RsvdP and
typically set by FW. In our case they are set by our RC host bridge
driver using internal registers.
Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx>
---
.../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 0925c520195a..f965ad57f32f 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -104,6 +104,18 @@ properties:
minItems: 1
maxItems: 3
+ brcm,gen3-eq-presets:
+ description: |
+ A u16 array giving the GEN3 equilization presets, one for each lane.
+ These values are destined for the 16bit registers known as the
+ Lane Equalization Control Register(s) of the Secondary PCI Express
+ Extended Capability. In the array, lane 0 is first term, lane 1 next,
+ etc. The contents of the entries reflect what is necessary for
+ the current board and SoC, and the details of each preset are
+ described in Section 7.27.4 of the PCI base spec, Revision 3.0.
If these are defined by the PCIe spec, then why is it Broadcom specific
property?
Hi Rob,
qcom pcie driver also needs to program these presets as you suggested
this can go to common pci bridge binding.
from PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4.2 for data rates
of 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s uses one class of preset (P0
through P10) and where as data rates of 64.0 GT/s use different class of
presets (Q0 through Q10) (Table 4-23). And data rates of 8.0 GT/s also
have optional preset hints (Table 4-24).
And there is possibility that for each data rate we may require
different preset configuration.
Can we have a dt binding for each data rate of 16 byte array.
like gen3-eq-preset array, gen4-eq-preset array etc.
- Krishna Chaitanya
+
+ $ref: /schemas/types.yaml#/definitions/uint16-array
minItems: 1
maxItems: 16
Last I saw, you can only have up to 16 lanes.
Rob
