On Tue, Oct 15, 2024 at 11:52:12PM -0700, Tomasz Jeznach wrote: > This patch series introduces support for RISC-V IOMMU architected > hardware into the Linux kernel. > > The RISC-V IOMMU specification, which this series is based on, is > ratified and available at GitHub/riscv-non-isa [1]. > > At a high level, the RISC-V IOMMU specification defines: > > 1) Data structures: > - Device-context: Associates devices with address spaces and holds > per-device parameters for address translations. > - Process-contexts: Associates different virtual address spaces based > on device-provided process identification numbers. > - MSI page table configuration used to direct an MSI to a guest > interrupt file in an IMSIC. > 2) In-memory queue interface: > - Command-queue for issuing commands to the IOMMU. > - Fault/event queue for reporting faults and events. > - Page-request queue for reporting "Page Request" messages received > from PCIe devices. > - Message-signaled and wire-signaled interrupt mechanisms. > 3) Memory-mapped programming interface: > - Mandatory and optional register layout and description. > - Software guidelines for device initialization and capabilities discovery. > > > This series introduces RISC-V IOMMU hardware initialization and complete > single-stage translation with paging domain support. > > The patches are organized as follows: > > Patch 1: Introduces minimal required device tree bindings for the driver. > Patch 2: Defines RISC-V IOMMU data structures, hardware programming interface > registers layout, and minimal initialization code for enabling global > pass-through for all connected masters. > Patch 3: Implements the device driver for PCIe implementation of RISC-V IOMMU > architected hardware. > Patch 4: Introduces IOMMU interfaces to the kernel subsystem. > Patch 5: Implements device directory management with discovery sequences for > I/O mapped or in-memory device directory table location, hardware > capabilities discovery, and device to domain attach implementation. > Patch 6: Implements command and fault queue, and introduces directory cache > invalidation sequences. > Patch 7: Implements paging domain, using highest page-table mode advertised > by the hardware. This series enables only 4K mappings; complete support > for large page mappings will be introduced in follow-up patch series. > > Follow-up patch series providing MSI interrupt remapping, complete ATS/PRI/SVA > and VFIO/IOMMUFD support are available at the GitHub [2], and has been tested > with published QEMU RISC-V IOMMU device model [3]. > > Changes from v9: > - rebase on v6.12-rc3 > - #6 Memory ordering fix and updated commentary, based on Will’s suggestions. > - #7 Remove riscv_iommu_device_domain_type() and use head-less kfree_rcu in > riscv_iommu_release_device(), based on Jason's suggestions. Thanks, looks ok to me now. Will
