在 10/18/2024 2:20 PM, Qingqing Zhou 写道:
>
>
> 在 10/18/2024 4:05 AM, Konrad Dybcio 写道:
>> On 15.10.2024 10:16 AM, Qingqing Zhou wrote:
>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
>>> to limit DMA address range to 36bit width to align with system
>>> architecture.
>>>
>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@xxxxxxxxxxx>
>>> ---
>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++
>>> 1 file changed, 74 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> index 027c5125f36b..fcba83fca7cf 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>>> @@ -379,6 +379,7 @@
>>> soc: soc@0 {
>>> compatible = "simple-bus";
>>> ranges = <0 0 0 0 0x10 0>;
>>> + dma-ranges = <0 0 0 0 0x10 0>;
>>> #address-cells = <2>;
>>> #size-cells = <2>;
>>>
>>> @@ -524,6 +525,79 @@
>>> reg = <0x0 0x0c3f0000 0x0 0x400>;
>>> };
>>>
>>> + apps_smmu: iommu@15000000 {
>>> + compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>>> + reg = <0x0 0x15000000 0x0 0x80000>;
>>> + #iommu-cells = <2>;
>>> + #global-interrupts = <1>;
>>> +
>>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
>>
>> The list seems perfectly sorted, which is suspicious.. if we set
>> i = n - #global-interrupts, interrupt[i] signifies an error in the i-th
>> context bank. If the order is wrong, we'll get bogus reports
> Thanks for the review, the list refers to Qualcomm Interrupts design spec, checking this platform again, the list is right, first line is global interrupt and the others are context interrupts with right order.
Hi Konrad,
Hope above comments explain your question. If no more questions from you, I will post the next version. Thanks.
>>
>> Also, this is not aligned properly ('<' under '<')
> Got it, will update and align the spaces in next version.
>>
>> Konrad
>
>
