On Thu, 2024-10-17 at 05:11 +0200, Marek Vasut wrote:
> The LVDS panel on this device uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1
> to 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout engine can
> reach accurate pixel clock of exactly 72.4 MHz.
>
> Without this patch, the Video PLL1 frequency is the default set in imx8mp.dtsi
> which is 1039.5 MHz, which divides down to inaccurate pixel clock of 74.25 MHz
> which works for this particular panel by sheer chance.
>
> Stop taking that chance and set correct accurate pixel clock frequency instead.
>
> Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support")
> Reported-by: Isaac Scott <isaac.scott@xxxxxxxxxxxxxxxx>
> Signed-off-by: Marek Vasut <marex@xxxxxxx>
Reviewed-by: Yannic Moog <y.moog@xxxxxxxxx>
Tested-by: Yannic Moog <y.moog@xxxxxxxxx>
> ---
> Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
> Cc: Fabio Estevam <festevam@xxxxxxxxx>
> Cc: Isaac Scott <isaac.scott@xxxxxxxxxxxxxxxx>
> Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
> Cc: Liu Ying <victor.liu@xxxxxxx>
> Cc: Pengutronix Kernel Team <kernel@xxxxxxxxxxxxxx>
> Cc: Rob Herring <robh@xxxxxxxxxx>
> Cc: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
> Cc: Yannic Moog <y.moog@xxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Cc: imx@xxxxxxxxxxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> ---
> Note: I do not have the board, but Isaac reported they tested it successfully.
> TB would be nice.
> ---
> .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> index 50debe821c421..9c102acb8052c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> @@ -218,6 +218,18 @@ ldb_lvds_ch1: endpoint {
> };
> };
>
> +&media_blk_ctrl {
> + /*
> + * The LVDS panel on this device uses 72.4 MHz pixel clock,
> + * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB
> + * serializer and LCDIFv3 scanout engine can reach accurate
> + * pixel clock of exactly 72.4 MHz.
> + */
> + assigned-clock-rates = <500000000>, <200000000>,
> + <0>, <0>, <500000000>,
> + <506800000>;
> +};
> +
> &snvs_pwrkey {
> status = "okay";
> };
