Hi Florian, On 10/14/24 20:07, Florian Fainelli wrote: > On 10/14/24 06:07, Stanimir Varbanov wrote: >> Use canned MDIO writes from Broadcom that switch the ref_clk output >> pair to run from the internal fractional PLL, and set the internal >> PLL to expect a 54MHz input reference clock. >> >> Without this RPi5 PCIe cannot enumerate endpoint devices on >> extension connector. > > You could say that the default reference clock for the PLL is 100MHz, > except for some devices, where it is 54MHz, like 2712d0. AFAIR, 2712c1 > might have been 100MHz as well, so whether we need to support that > revision of the chip or not might be TBD. I'm confused now, according to [1] : BCM2712C1 - 4GB and 8GB RPi5 models BCM2712D0 - 2GB RPi5 models My device is 4GB RPi5 model so I would expect it is BCM2712C1, thus according to your comment the PLL PHY adjustment is not needed. But I see that the PCIex1 RC cannot enumerate devices on ext PCI connector because of link training failure. Implementing PLL adjustment fixes the failure. ~Stan [1] https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
