On Mon, Sep 02, 2024 at 06:01:35PM +0300, Abel Vesa wrote:
> The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports,
> all of them supporting external DP altmode. Between each QMP
> combo PHY and the corresponding Type-C port, sits one Parade PS8830
> retimer which handles both orientation and SBU muxing. Add nodes for
> each retimer, fix the graphs between connectors and the PHYs accordingly,
> add the voltage regulators needed by each retimer and then enable all
> 3 remaining DPUs.
> +&i2c1 {
> + clock-frequency = <400000>;
> +
> + status = "okay";
> +
> + typec-mux@8 {
> + compatible = "parade,ps8830";
> + reg = <0x08>;
> +
> + clocks = <&rpmhcc RPMH_RF_CLK5>;
> + clock-names = "xo";
> +
> + vdd15-supply = <&vreg_rtmr2_1p15>;
> + vdd18-supply = <&vreg_rtmr2_1p8>;
> + vdd33-supply = <&vreg_rtmr2_3p3>;
> +
> + reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>;
pincfg missing
> +&i2c3 {
> + clock-frequency = <400000>;
> +
> + status = "okay";
> +
> + typec-mux@8 {
> + compatible = "parade,ps8830";
> + reg = <0x08>;
> +
> + clocks = <&rpmhcc RPMH_RF_CLK3>;
> + clock-names = "xo";
> +
> + vdd15-supply = <&vreg_rtmr0_1p15>;
> + vdd18-supply = <&vreg_rtmr0_1p8>;
> + vdd33-supply = <&vreg_rtmr0_3p3>;
> +
> + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>;
Same here.
> +&i2c7 {
> + clock-frequency = <400000>;
> +
> + status = "okay";
> +
> + typec-mux@8 {
> + compatible = "parade,ps8830";
> + reg = <0x8>;
> +
> + clocks = <&rpmhcc RPMH_RF_CLK4>;
> + clock-names = "xo";
> +
> + vdd15-supply = <&vreg_rtmr1_1p15>;
> + vdd18-supply = <&vreg_rtmr1_1p8>;
> + vdd33-supply = <&vreg_rtmr1_3p3>;
> +
> + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>;
And here.
Johan
