On Tue, Oct 15, 2024 at 1:50 AM Will Deacon <will@xxxxxxxxxx> wrote: > > On Thu, Oct 10, 2024 at 12:48:05PM -0700, Tomasz Jeznach wrote: > > Introduce platform device driver for implementation of RISC-V IOMMU > > architected hardware. > > > > Hardware interface definition located in file iommu-bits.h is based on > > ratified RISC-V IOMMU Architecture Specification version 1.0.0. > > > > This patch implements platform device initialization, early check and > > configuration of the IOMMU interfaces and enables global pass-through > > address translation mode (iommu_mode == BARE), without registering > > hardware instance in the IOMMU subsystem. > > > > Link: https://github.com/riscv-non-isa/riscv-iommu > > Co-developed-by: Nick Kossifidis <mick@xxxxxxxxxxxx> > > Signed-off-by: Nick Kossifidis <mick@xxxxxxxxxxxx> > > Co-developed-by: Sebastien Boeuf <seb@xxxxxxxxxxxx> > > Signed-off-by: Sebastien Boeuf <seb@xxxxxxxxxxxx> > > Reviewed-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx> > > Signed-off-by: Tomasz Jeznach <tjeznach@xxxxxxxxxxxx> > > --- > > [...] > > > diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h > > new file mode 100644 > > index 000000000000..700e33dc2446 > > --- /dev/null > > +++ b/drivers/iommu/riscv/iommu.h > > @@ -0,0 +1,62 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright © 2022-2024 Rivos Inc. > > + * Copyright © 2023 FORTH-ICS/CARV > > + * > > + * Authors > > + * Tomasz Jeznach <tjeznach@xxxxxxxxxxxx> > > + * Nick Kossifidis <mick@xxxxxxxxxxxx> > > + */ > > + > > +#ifndef _RISCV_IOMMU_H_ > > +#define _RISCV_IOMMU_H_ > > + > > +#include <linux/iommu.h> > > +#include <linux/types.h> > > +#include <linux/iopoll.h> > > + > > +#include "iommu-bits.h" > > + > > +struct riscv_iommu_device { > > + /* iommu core interface */ > > + struct iommu_device iommu; > > + > > + /* iommu hardware */ > > + struct device *dev; > > + > > + /* hardware control register space */ > > + void __iomem *reg; > > + > > + /* supported and enabled hardware capabilities */ > > + u64 caps; > > + u32 fctl; > > + > > + /* available interrupt numbers, MSI or WSI */ > > + unsigned int irqs[RISCV_IOMMU_INTR_COUNT]; > > + unsigned int irqs_count; > > +}; > > + > > +int riscv_iommu_init(struct riscv_iommu_device *iommu); > > +void riscv_iommu_remove(struct riscv_iommu_device *iommu); > > + > > +#define riscv_iommu_readl(iommu, addr) \ > > + readl_relaxed((iommu)->reg + (addr)) > > + > > +#define riscv_iommu_readq(iommu, addr) \ > > + readq_relaxed((iommu)->reg + (addr)) > > + > > +#define riscv_iommu_writel(iommu, addr, val) \ > > + writel_relaxed((val), (iommu)->reg + (addr)) > > + > > +#define riscv_iommu_writeq(iommu, addr, val) \ > > + writeq_relaxed((val), (iommu)->reg + (addr)) > > + > > +#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ > > + readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \ > > + delay_us, timeout_us) > > + > > +#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ > > + readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ > > + delay_us, timeout_us) > > + > > +#endif > > Curious: why do you need these MMIO wrappers if the driver depends on > 64BIT? > Hello Will, These wrappers were initially created to support 32-bit CPU architectures but were later discontinued to concentrate on practical driver use cases. It has been observed that some RISC-V IOMMU hardware implementations might only allow 32-bit MMIO access, even on 64-bit systems. The wrappers are left in place to accommodate these potential designs if they arise. I'd leave them for now and reevaluate their necessity in a few months. Thanks, - Tomasz > Will
