This patch series introduces support for RISC-V IOMMU architected
hardware into the Linux kernel.
The RISC-V IOMMU specification, which this series is based on, is
ratified and available at GitHub/riscv-non-isa [1].
At a high level, the RISC-V IOMMU specification defines:
1) Data structures:
- Device-context: Associates devices with address spaces and holds
per-device parameters for address translations.
- Process-contexts: Associates different virtual address spaces based
on device-provided process identification numbers.
- MSI page table configuration used to direct an MSI to a guest
interrupt file in an IMSIC.
2) In-memory queue interface:
- Command-queue for issuing commands to the IOMMU.
- Fault/event queue for reporting faults and events.
- Page-request queue for reporting "Page Request" messages received
from PCIe devices.
- Message-signaled and wire-signaled interrupt mechanisms.
3) Memory-mapped programming interface:
- Mandatory and optional register layout and description.
- Software guidelines for device initialization and capabilities discovery.
This series introduces RISC-V IOMMU hardware initialization and complete
single-stage translation with paging domain support.
The patches are organized as follows:
Patch 1: Introduces minimal required device tree bindings for the driver.
Patch 2: Defines RISC-V IOMMU data structures, hardware programming interface
registers layout, and minimal initialization code for enabling global
pass-through for all connected masters.
Patch 3: Implements the device driver for PCIe implementation of RISC-V IOMMU
architected hardware.
Patch 4: Introduces IOMMU interfaces to the kernel subsystem.
Patch 5: Implements device directory management with discovery sequences for
I/O mapped or in-memory device directory table location, hardware
capabilities discovery, and device to domain attach implementation.
Patch 6: Implements command and fault queue, and introduces directory cache
invalidation sequences.
Patch 7: Implements paging domain, using highest page-table mode advertised
by the hardware. This series enables only 4K mappings; complete support
for large page mappings will be introduced in follow-up patch series.
Follow-up patch series providing MSI interrupt remapping, complete ATS/PRI/SVA
and VFIO/IOMMUFD support are available at the GitHub [2], and has been tested
with published QEMU RISC-V IOMMU device model [3].
Changes from v8:
- rebase on v6.12-rc2
- #1 MAINTAINERS file updated to point out IOMMU subsystem source repository location.
- #3 Update PCIe device IDs, use Red-Hat assigned VID:DID for QEMU RISC-V IOMMU model,
Update Rivos PCIe IOMMU hardware VID:DID.
- #7 Fix incorrect pgsize calculation in riscv_iommu_map_pages().
Fix supported page size reporting for paging domain.
Fix boolean type for riscv_iommu_domain.amo_enabled.
Remove workaround for dev == NULL in ops->domain_alloc_paging, no longer needed
with domain allocation interface refactoring patches [4].
Best regards,
Tomasz Jeznach
[1] link: https://github.com/riscv-non-isa/riscv-iommu
[2] link: https://github.com/tjeznach/linux/riscv_iommu.next
[3] link: https://lore.kernel.org/qemu-devel/20241004155721.2154626-1-dbarboza@xxxxxxxxxxxxxxxx/
[4] link: https://lore.kernel.org/linux-iommu/20241009041147.28391-1-baolu.lu@xxxxxxxxxxxxxxx/
v8 link: https://lore.kernel.org/linux-iommu/cover.1718388908.git.tjeznach@xxxxxxxxxxxx/
v7 link: https://lore.kernel.org/linux-iommu/cover.1717612298.git.tjeznach@xxxxxxxxxxxx/
v6 link: https://lore.kernel.org/linux-iommu/cover.1716578450.git.tjeznach@xxxxxxxxxxxx/
v5 link: https://lore.kernel.org/linux-iommu/cover.1715708679.git.tjeznach@xxxxxxxxxxxx/
v4 link: https://lore.kernel.org/linux-iommu/cover.1714752293.git.tjeznach@xxxxxxxxxxxx/
v3 link: https://lore.kernel.org/linux-iommu/cover.1714494653.git.tjeznach@xxxxxxxxxxxx/
v2 link: https://lore.kernel.org/linux-iommu/cover.1713456597.git.tjeznach@xxxxxxxxxxxx/
v1 link: https://lore.kernel.org/linux-iommu/cover.1689792825.git.tjeznach@xxxxxxxxxxxx/
Tomasz Jeznach (7):
dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU
iommu/riscv: Add RISC-V IOMMU platform device driver
iommu/riscv: Add RISC-V IOMMU PCIe device driver
iommu/riscv: Enable IOMMU registration and device probe.
iommu/riscv: Device directory management.
iommu/riscv: Command and fault queue support
iommu/riscv: Paging domain support
.../bindings/iommu/riscv,iommu.yaml | 147 ++
MAINTAINERS | 9 +
drivers/iommu/Kconfig | 1 +
drivers/iommu/Makefile | 2 +-
drivers/iommu/riscv/Kconfig | 20 +
drivers/iommu/riscv/Makefile | 3 +
drivers/iommu/riscv/iommu-bits.h | 784 ++++++++
drivers/iommu/riscv/iommu-pci.c | 120 ++
drivers/iommu/riscv/iommu-platform.c | 92 +
drivers/iommu/riscv/iommu.c | 1656 +++++++++++++++++
drivers/iommu/riscv/iommu.h | 88 +
11 files changed, 2921 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
create mode 100644 drivers/iommu/riscv/Kconfig
create mode 100644 drivers/iommu/riscv/Makefile
create mode 100644 drivers/iommu/riscv/iommu-bits.h
create mode 100644 drivers/iommu/riscv/iommu-pci.c
create mode 100644 drivers/iommu/riscv/iommu-platform.c
create mode 100644 drivers/iommu/riscv/iommu.c
create mode 100644 drivers/iommu/riscv/iommu.h
base-commit: 8cf0b93919e13d1e8d4466eb4080a4c4d9d66d7b
--
2.34.1
