On 10/11/24 14:38, Marek Vasut wrote:
On 10/11/24 2:07 PM, Gatien CHEVALLIER wrote:
On 10/11/24 13:24, Marek Vasut wrote:
On 10/11/24 11:55 AM, Gatien CHEVALLIER wrote:
On 10/7/24 15:54, Marek Vasut wrote:
On 10/7/24 3:27 PM, Gatien Chevallier wrote:
Implement the support for STM32MP25x platforms. On this platform, a
security clock is shared between some hardware blocks. For the RNG,
it is the RNG kernel clock. Therefore, the gate is no more shared
between the RNG bus and kernel clocks as on STM32MP1x platforms and
the bus clock has to be managed on its own.
Signed-off-by: Gatien Chevallier <gatien.chevallier@xxxxxxxxxxx>
A bit of a higher-level design question -- can you use drivers/clk/
clk-bulk.c clk_bulk_*() to handle all these disparate count of
clock easily ?
Hi, I'd like to make sure that we enable the core clock before the bus
clock so that the RNG hardware block can start its internal tests while
we ungate the bus clock. It's not a strong opinion but it feels better.
Maybe this could still work if the struct clk_bulk_data {} is ordered
that way, so the bus clock are first, and the rest afterward ?
I guess you meant, the core first.
Err, yes, core.
Putting the bus clock first with the updated YAML doc generates a
warning when checking the bindings. I guess what you propose is OK
then. Core clock is defined first in the device tree.
Not in DT, leave DT as-is. Look at struct clk_bulk_data , I think when
you use the clk_bulk_*() functions, you pass in a list of struct
clk_bulk_data, which each describes one clock, so just make sure that
list of struct clk_bulk_data in the driver is ordered the way you need
it to be ordered and you should be fine.
I've sent a V2 with something that is functional but not aesthetic.
You'll tell me if that's what you had in mind.
Best regards,
Gatien
