> > The ASPEED AST27XX interrupt controller(INTC) contain second level and > > third level interrupt controller. > > > > INTC0: > > The second level INTC, which used to assert GIC(#192~#197) if > > interrupt in INTC1 asserted. There are 6 GIC interrupt > > number(#192~#197) used in one INTC0. > > > > INTC1_x: > > The third level INTC, which used to assert GIC(#192~#197) if interrupt > > in > > INTC1 asserted. There are 6 GIC interrupt number(#192~#197) used in one > INTC0. > > > > Signed-off-by: Kevin Chen <kevin_chen@xxxxxxxxxxxxxx> > > --- > > .../aspeed,ast2700-intc.yaml | 87 > +++++++++++++++++++ > > 1 file changed, 87 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700- > > intc.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270 > > 0-intc.yaml > > b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270 > > 0-intc.yaml > > new file mode 100644 > > index 000000000000..650a1f6e1177 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,as > > +++ t2700-intc.yaml > > @@ -0,0 +1,87 @@ > > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause %YAML 1.2 > > +--- > > +$id: > > +http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int > > +c.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Aspeed AST2700 Interrupt Controller > > + > > +description: > > + This interrupt controller hardware is second level interrupt > > +controller that > > + is hooked to a parent interrupt controller. It's useful to combine > > +multiple > > + interrupt sources into 1 interrupt to parent interrupt controller. > > + > > +maintainers: > > + - Kevin Chen <kevin_chen@xxxxxxxxxxxxxx> > > + > > +properties: > > + compatible: > > + enum: > > + - aspeed,ast2700-intc-ic > > + > > + reg: > > + maxItems: 1 > > + > > + interrupt-controller: true > > + > > + '#interrupt-cells': > > + const: 2 > > Describe the meaning of the cells here. I would change to the following code + '#interrupt-cells': + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. > > > + > > + interrupts: > > + maxItems: 10 > > + description: > > You need '|' to preserve formatting. OK. Thanks > > > + Depend to which INTC0 or INTC1 used. > > + INTC0 and INTC1 are two kinds of interrupt controller with enable > and raw > > + status registers for use. > > + INTC0 is used to assert GIC if interrupt in INTC1 asserted. > > + INTC1 is used to assert INTC0 if interrupt of modules asserted. > > + +-----+ +-------+ +---------+---module0 > > + | GIC |---| INTC0 |--+--| INTC1_0 |---module2 > > + | | | | | | |---... > > + +-----+ +-------+ | +---------+---module31 > > + | > > + | +---------+---module0 > > + +---| INTC1_1 |---module2 > > + | | |---... > > + | +---------+---module31 > > + ... > > + | +---------+---module0 > > + +---| INTC1_5 |---module2 > > + | |---... > > + +---------+---module31 > > + > > + > > +required: > > + - compatible > > + - reg > > + - interrupt-controller > > + - '#interrupt-cells' > > + - interrupts > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + bus { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + interrupt-controller@12101b00 { > > + compatible = "aspeed,ast2700-intc-ic"; > > + reg = <0 0x12101b00 0 0x10>; > > + #interrupt-cells = <2>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > -- > > 2.34.1 > >
