Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@xxxxxxxxxxxx>
> ---
[snip]
> +
> +static void set_fifo_threshold(void __iomem *dma_base)
> +{
> + u32 fifo_size = 0;
> +
> + fifo_size = readl_relaxed(dma_base + DMA_OFFSET_CON0) & 0xFFF;
> + writel_relaxed((0x1 << 28) |
> + ((fifo_size * 1 / 4) & 0xFFF) << 16 |
> + ((fifo_size * 1 / 8) & 0xFFF),
> + dma_base + DMA_OFFSET_CON1);
I can not find definition of DMA_OFFSET_CON1 in this patch, but I find it in [6/10] patch.
Move the definition to this patch.
And when you add this file, make sure you could build it successfully.
Regards,
CK
> + writel_relaxed((0x1 << 28) |
> + ((fifo_size * 1 / 2) & 0xFFF) << 16 |
> + ((fifo_size * 3 / 8) & 0xFFF),
> + dma_base + DMA_OFFSET_CON2);
> + writel_relaxed((0x1 << 31) |
> + ((fifo_size * 2 / 3) & 0xFFF) << 16 |
> + ((fifo_size * 13 / 24) & 0xFFF),
> + dma_base + DMA_OFFSET_CON3);
> + writel_relaxed((0x1 << 31) |
> + ((fifo_size * 3 / 8) & 0xFFF) << 16 |
> + ((fifo_size * 1 / 4) & 0xFFF),
> + dma_base + DMA_OFFSET_CON4);
> +}
> +
