On Thu 2024-10-10 @ 12:19:41 PM, Dragan Simic wrote:
> Until the TSADC, thermal zones, thermal trips and cooling maps are defined
> in the RK3308 SoC dtsi, none of the CPU OPPs except the slowest one may be
> enabled under any circumstances. Allowing the DVFS to scale the CPU cores
> up without even just the critical CPU thermal trip in place can rather easily
> result in thermal runaways and damaged SoCs, which is bad.
>
> Thus, leave only the lowest available CPU OPP enabled for now.
>
It builds, it runs, it's been running on one of my rock-pi-s boards for ~3h
now. I can read my spi, i2c, and w1 sensors, so no issues for me.
# cat /sys/bus/cpu/devices/cpu*/cpufreq/stats/time_in_state
408000 1168942
408000 1168942
408000 1168942
408000 1168942
Tested-by: Trevor Woerner <twoerner@xxxxxxxxx>
> Fixes: 6913c45239fd ("arm64: dts: rockchip: Add core dts for RK3308 SOC")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Dragan Simic <dsimic@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/rockchip/rk3308.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
> index 31c25de2d689..a7698e1f6b9e 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
> @@ -120,16 +120,19 @@ opp-600000000 {
> opp-hz = /bits/ 64 <600000000>;
> opp-microvolt = <950000 950000 1340000>;
> clock-latency-ns = <40000>;
> + status = "disabled";
> };
> opp-816000000 {
> opp-hz = /bits/ 64 <816000000>;
> opp-microvolt = <1025000 1025000 1340000>;
> clock-latency-ns = <40000>;
> + status = "disabled";
> };
> opp-1008000000 {
> opp-hz = /bits/ 64 <1008000000>;
> opp-microvolt = <1125000 1125000 1340000>;
> clock-latency-ns = <40000>;
> + status = "disabled";
> };
> };
>
>
