On 2024-10-10 12:19, Dragan Simic wrote:
Until the TSADC, thermal zones, thermal trips and cooling maps are
defined
in the RK3308 SoC dtsi, none of the CPU OPPs except the slowest one may
be
enabled under any circumstances. Allowing the DVFS to scale the CPU
cores
up without even just the critical CPU thermal trip in place can rather
easily
result in thermal runaways and damaged SoCs, which is bad.
Thus, leave only the lowest available CPU OPP enabled for now.
Fixes: 6913c45239fd ("arm64: dts: rockchip: Add core dts for RK3308
SOC")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Dragan Simic <dsimic@xxxxxxxxxxx>
As a note, I'll hopefully get back with the proper implementation of the
thermal configuration for the RK3308, but not before the 6.14 merge
window.
In the meantime, let's stick to having only the lowest CPU OPP in place,
as changed in this patch.
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 31c25de2d689..a7698e1f6b9e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -120,16 +120,19 @@ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1340000>;
clock-latency-ns = <40000>;
+ status = "disabled";
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1025000 1025000 1340000>;
clock-latency-ns = <40000>;
+ status = "disabled";
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1125000 1125000 1340000>;
clock-latency-ns = <40000>;
+ status = "disabled";
};
};
